A clock distribution chip (also referred to as a clock chip) is an integrated circuit (IC) designed to distribute clock signals to other electronic devices, such as other devices located on the same printed circuit board (PCB) as the clock distribution chip. Traditionally, there have been two different types of clock distribution chips: (1) zero-delay buffers and (2) non-zero-delay buffers (also referred to as simple clock buffers or drivers).
A zero-delay buffer receives an input (i.e., reference) clock signal and generates multiple output clock signals having specified (e.g., zero) phase offsets relative to the input clock signal. Zero-delay buffers typically employ phase-locked loops (PLLs) to generate the output clock signals, where the frequency of each output clock signal may differ from (e.g., may be greater or smaller than) the frequency of the reference clock signal. Some PLL-based zero-delay buffers offer skew control to select desired, non-zero phase offsets for one or more of the output clock signals relative to the reference clock signal.
Non-zero-delay buffers provide multiple copies of an input clock signal without ensuring that the generated output clock signals have any predictable phase offsets relative to the input clock signal. Non-zero-delay buffers are typically non-PLL-based circuits.
In order for different devices, e.g., located on a single PCB, to be able to communicate, each transmitting device must transmit signals that each corresponding receiving device will recognize. Signaling standards have been promulgated to specify the characteristics of signals to enable such inter-device communications. Some signaling standards, such as LVPECL and LVDS, involve differential clock signals, while other signaling standards, such as LVTTL, LVCMOS, HSTL, and SSTL, involve single-ended (SE) clock signals. In addition, different signaling standards involve different voltage amplitudes, including some individual signaling standards having different versions at different voltage amplitudes. For example, there are three different types of LVCMOS signaling that are based on 1.8V, 2.5V, and 3.3V amplitudes, respectively.
Conventional zero-delay buffers and conventional non-zero-delay buffers come in particular models, each of which receives a limited variety of input clock signals and generates a limited variety of output clock signals (e.g., different models for different voltage amplitudes). For many applications, PCBs have different devices that require different clock signals, e.g., conforming to different signaling standards, for their processing, where some devices may require zero-delay clock signals, while other devices might not be able to tolerate the jitter typically inherent in PLL-generated zero-delay clock signals. As a result, a PCB for such an application is typically configured with a relatively large number of different models of clock distribution chips in order to support the variety of different signaling standards required by the devices on that PCB, resulting in possible wastage of resources.